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FINAL
COM'L: -12/15/20, Q-20/25
MACH435-12/15/20, Q-20/25
High-Density EE CMOS Programmable Logic
DISTINCTIVE CHARACTERISTICS
s 84 Pins in PLCC s 128 Macrocells s 12 ns tPD s 83.3 MHz fCNT s 70 Inputs with pull-up resistors s 64 Outputs s 192 Flip-flops -- 128 Macrocell flip-flops -- 64 Input flip-flops s Up to 20 product terms per function, with XOR
Lattice Semiconductor
s Flexible clocking -- Four global clock pins with selectable edges -- Asynchronous mode available for each macrocell s 8 "PAL33V16" blocks s Input and output switch matrices for high routability s Fixed, predictable, deterministic delays s Pin compatible with MACH130, MACH131, MACH230, and MACH231
GENERAL DESCRIPTION
The MACH435 is a member of our high-performance EE CMOS MACH 4 family. This device has approximately twelve times the macrocell capability of the popular PAL22V10, with significant density and functional features that the PAL22V10 does not provide. The MACH435 consists of eight PAL blocks interconnected by a programmable central switch matrix. The central switch matrix connects the PAL blocks to each other and to all input pins, providing a high degree of connectivity between the fully-connected PAL blocks. This allows designs to be placed and routed efficiently. Routability is further enhanced by an input switch matrix and an output switch matrix. The input switch matrix provides input signals with alternative paths into the central switch matrix; the output switch matrix provides flexibility in assigning macrocells to I/O pins. The MACH435 has macrocells that can be configured as synchronous or asynchronous. This allows designers to implement both synchronous and asynchronous logic together on the same device. The two types of design can be mixed in any proportion, since the selection on each macrocell affects only that macrocell. Up to 20 product terms per function can be assigned. It is possible to allocate some product terms away from a macrocell without losing the use of that macrocell for logic generation. The MACH435 macrocell provides either registered or combinatorial outputs with programmable polarity. If a registered configuration is chosen, the register can be configured as D-type, T-type, J-K, or S-R to help reduce the number of product terms used. The flip-flop can also be configured as a latch. The register type decision can be made by the designer or by the software. All macrocells can be connected to an I/O cell through the output switch matrix. The output switch matrix makes it possible to make significant design changes while minimizing the risk of pinout changes.
Publication# 17469 Rev. E Issue Date: May 1995
Amendment /0
2
I/O0-I/O7 I/O8-I/O15 I/O16-I/O23 I/O24-I/031 8 8 I/O Cells 4 8 4 16 Macrocells OE 16 Output Switch Matrix 8 I/O Cells 8 4 8 16 16 Macrocells OE OE 16 4 16 Macrocells 4 16 16 16 4 16 Output Switch Matrix 8 Output Switch Matrix 4 Output Switch Matrix 16 16 16 Macrocells 16 Input Switch Matrix Input Switch Matrix Input Switch Matrix 4 66 X 90 AND Logic Array and Logic Allocator 24 33 24 33 66 X 90 AND Logic Array and Logic Allocator 4 8 8 I/O Cells I/O Cells 8 8 Clock Generator Clock Generator Clock Generator 16 16 Input Switch Matrix 66 X 90 AND Logic Array and Logic Allocator 33 24 33 24 I2, I5
BLOCK DIAGRAM
4
4
Clock Generator
8
4
OE
66 X 90 AND Logic Array and Logic Allocator
4 33 24 33 24 33
Central Switch Matrix
24 33 24
CLK0/I0, CLK1/I1, CLK2/I3, CLK3/I4 4 OE 4 OE
4
2
MACH435-12/15/20, Q-20/25
Input Switch Matrix Input Switch Matrix Input Switch Matrix 66 X 90 AND Logic Array and Logic Allocator 16 Macrocells 16 16 Output Switch Matrix 8 I/O Cells 8 4 8 I/O Cells 8 16 8 Output Switch Matrix 4 16 16 16 4 8 4 66 X 90 AND Logic Array and Logic Allocator 16 Macrocells 16 16 Output Switch Matrix 8 I/O Cells 8 16 16 Macrocells Clock Generator Clock Generator I/O48-I/O55 I/O40-I/O47
Input Switch Matrix
4
66 X 90 AND Logic Array and Logic Allocator
4 OE
66 X 90 AND Logic Array and Logic Allocator 16 Macrocells 4 8 4
4
Clock Generator
Clock Generator
4
OE
16 16 Output Switch Matrix 8 I/O Cells 8 16
8
17469E-1
I/O56-I/O63
I/O32-I/O39
CONNECTION DIAGRAM Top View PLCC
GND I/O7 I/O6 I/O5 I/O4 I/O3 I/O2 I/O1 I/O0 VCC GND VCC I5 I/O63 I/O62 I/O61 I/O60 I/O59 I/O58 I/O57 I/O56 GND I/O55 I/O54 I/O53 I/O52 I/O51 I/O50 I/O49 I/O48 CLK3/I4 GND VCC CLK2/I3 I/O47 I/O46 I/O45 I/O44 I/O43 I/O42 I/O41 I/O40 I/O32 I/O33 I/O34 I/O35 I/O36 I/O37 I/O38 I/O39 GND
I/O8 I/O9 I/O10 I/O11 I/O12 I/O13 I/O14 I/O15 CLK0/I0 VCC GND CLK1/I1 I/O16 I/O17 I/O18 I/O19 I/O20 I/O21 I/O22 I/O23 GND
11 10 9 8 7 6 5 4 3 2 1 84 83 82 81 80 79 78 77 76 75 74 12 13 73 72 14 71 15 70 16 17 69 68 18 67 19 66 20 21 65 64 22 63 23 62 24 61 25 60 26 27 59 58 28 57 29 56 30 55 31 54 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 I/O24 I/O25 I/O26 I/O27 I/O28 I/O29 I/O30 I/O31 I2 VCC GND VCC
17469E-2
Note: Pin-compatible with MACH130, MACH131, MACH230, and MACH231
PIN DESIGNATIONS
CLK/I GND I I/O VCC = = = = = Clock or Input Ground Input Input/Output Supply Voltage
MACH435-12/15/20, Q-20/25
3
ORDERING INFORMATION Commercial Products
Programmable logic products for commercial applications are available with several ordering options. The order number (Valid Combination) is formed by a combination of:
MACH 435 -12
J
C
FAMILY TYPE MACH = Macro Array CMOS High-Speed DEVICE NUMBER 435 = 2nd Generation, 128 Macrocells, 84 Pins 435Q = 2nd Generation, 128 Macrocells, 84 Pins, Quarter Power SPEED -12 = 12 ns tPD -15 = 15 ns tPD -20 = 20 ns tPD -25 = 25 ns tPD
OPTIONAL PROCESSING Blank = Standard Processing
OPERATING CONDITIONS C = Commercial (0C to +70C) PACKAGE TYPE J = 84-Pin Plastic Leaded Chip Carrier (PL 084)
Valid Combinations MACH435-12 MACH435-15 MACH435-20 MACH435Q-20 MACH435Q-25
JC
Valid Combinations The Valid Combinations table lists configurations planned to be supported in volume for this device. Consult your local sales office to confirm availability of specific valid combinations and to check on newly released combinations.
4
MACH435-12/15/20, Q-20/25
FUNCTIONAL DESCRIPTION
The MACH435 consists of eight PAL blocks connected by a central switch matrix. There are 64 I/O pins and 6 dedicated input pins feeding the central switch matrix. These signals are distributed to the eight PAL blocks for efficient design implementation. There are 4 global clock pins that can also be used as dedicated inputs. All inputs and I/O pins have built-in pull-up resistors. While it is always good design practice to tie unused pins high, the pull-up resistors provide design security and stability in the event that unused pins are left disconnected.
The Product-Term Array
The MACH435 product-term array consists of 80 product terms for logic use, eight product terms for output enable use, and two product terms for global PAL block initialization. Each macrocell has a nominal allocation of 5 product terms for logic, although the logic allocator allows for logic redistribution. Each I/O pin has its own individual output enable term. The initialization product terms provide asynchronous reset or preset to synchronous-mode macrocells in the PAL block.
The Logic Allocator
The logic allocator in the MACH435 takes the 80 logic product terms and allocates them to the 16 macrocells as needed. Each macrocell can be driven by up to 20 product terms if in synchronous mode, or 18 product terms if in asynchronous mode. When product terms are routed away from a macrocell, it is possible to route all 5 product terms away, which precludes the use of the macrocell for logic generation; or it is possible to route only 4 product terms away, leaving one for simple function generation. The design software automatically configures the logic allocator when fitting the design into the device. The logic allocator also provides an exclusive-OR gate. This gate allows generation of combinatorial exclusiveOR logic, such as comparison or addition. It allows registered exclusive-OR functions, such as CRC generation, to be implemented more efficiently. It also makes in possible to emulate all flip-flop types with a D-type flip-flop. Register type emulation is automatically handled by the design software. Table 1 illustrates which product term clusters are available to each macrocell within a PAL block. Refer to Figure 1 for cluster and macrocell numbers.
The PAL Blocks
Each PAL block in the MACH435 (Figure 1) contains a clock generator, a 90-product-term logic array, a logic allocator, 16 macrocells, an output switch matrix, 8 I/O cells, and an input switch matrix. The central switch matrix feeds each PAL block with 33 inputs. This makes the PAL block look effectively like an independent "PAL33V16" with 8 to 16 buried macrocells. In addition to the logic product terms, individual output enable product terms and two PAL block initialization product term are provided. Each I/O pin can be individually enabled. All flip-flops that are in the synchronous mode within a PAL block are initialized together by either of the PAL block initialization product terms.
The Central Switch Matrix and Input Switch Matrix
The MACH435 central switch matrix is fed by the input switch matrices in each PAL block. Each PAL block provides 16 internal feedback signals, 8 registered input signals, and 8 I/O pin signals to the input switch matrix. Of these 32 signals, 24 decoded signals are provided to the central switch matrix by the input switch matrix. The central switch matrix distributes these signals back to the PAL blocks in a very efficient manner that provides for high performance. The design software automatically configures the input and central switch matrices when fitting a design into the device.
The Clock Generator
Each PAL block has a clock generator that can generate four clock signals for use throughout the PAL block. These four signals are available to all macrocells and I/O cells in the PAL block, whether in synchronous or asynchronous mode. The clock generator chooses the four signals from the eight possible signals given by the true and complement versions of the four global clock pin signals.
MACH435-12/15/20, Q-20/25
5
Table 1. Logic Allocation
Macrocell M0 M1 M2 M3 M4 M5 M6 M7 M8 M9 M10 M11 M12 M13 M14 M15 Available Clusters C0, C1, C2 C0, C1, C2, C3 C1, C2, C3, C4 C2, C3, C4, C5 C3, C4, C5, C6 C4, C5, C6, C7 C5, C6, C7, C8 C6, C7, C8, C9 C7, C8, C9, C10 C8, C9, C10, C11 C9, C10, C11, C12 C10, C11, C12, C13 C11, C12, C13, C14 C12, C13, C14, C15 C13, C14, C15 C14, C15
The macrocells can be configured as registered, latched, or combinatorial. In combination with the logic allocator, the registered configuration can be any of the standard flip-flop types. The macrocell provides internal feedback whether configured with or without the flipflop, and whether or not the macrocell drives an I/O cell. The flip-flop clock depends on the mode selected for the macrocell. In synchronous mode, any of the PAL block clocks generated by the Clock Generator can be used. In asynchronous mode, the additional choice of either edge of an individual product-term clock is available. Initialization can be handled as part of a bank of macrocells via the PAL block initialization terms if in synchronous mode, or individually if in asynchronous mode. In synchronous mode, one of the PAL block product terms is available each for preset and reset. The swap function determines which product term drives which function. This allows initialization polarity compatibility with the MACH 1 and 2 series. In asynchronous mode, one product term can be used either to drive reset or preset.
The Macrocell and Output Switch Matrix
The MACH435 has 16 macrocells, half of which can drive I/O pins; this selection is made by the output switch matrix. Each macrocell can drive one of four I/O cells. The allowed combinations are shown in Table 2. Please refer to Figure 1 for macrocell and I/O pin numbers. Table 2. Output Switch Matrix Combinations
Macrocell M0, M1 M2, M3 M4, M5 M6, M7 M8, M9 M10, M11 M12, M13 M14, M15 I/O Pin I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 Routable to I/O Pins I/O5, I/O6, I/O7, I/O0 I/O6, I/O7, I/O0, I/O1 I/O7, I/O0, I/O1, I/O2 I/O0, I/O1, I/O2, I/O3 I/O1, I/O2, I/O3, I/O4 I/O2, I/O3, I/O4, I/O5 I/O3, I/O4, I/O5, I/O6 I/O4, I/O5, I/O6, I/O7 Available Macrocells M0, M1, M2, M3, M4, M5, M6, M7 M2, M3, M4, M5, M6, M7, M8, M9 M4, M5, M6, M7, M8, M9, M10, M11 M6, M7, M8, M9, M10, M11, M12, M13 M8, M9, M10, M11, M12, M13, M14, M15 M10, M11, M12, M13, M14, M15, M0, M1 M12, M13, M14, M15, M0, M1, M2, M3 M14, M15, M0, M1, M2, M3, M4, M5
The I/O Cell
The I/O cell in the MACH435 consists of a three-state buffer and an input flip-flop. The I/O cell is driven by one of the macrocells, as selected by the output switch matrix. Each I/O cell can take its input from one of eight macrocells. The three-state buffer is controlled by an individual product term. The input flip-flop can be configured as a register or latch. Both the direct I/O signal and the registered/latched signal are available to the input switch matrix, and can be used simultaneously if desired.
6
MACH435-12/15/20, Q-20/25
CLK0/I0 CLK1/I1
16
Clock Generator
4
CLK2/I3 CLK3/I4
C0
M0
Macrocell
M0
O0
I/O Cell
I/O0
C1
M1
Macrocell
M1
C2
M2
Macrocell
M2
O1
I/O Cell
I/O1
C3
M3
Macrocell
M3
C4
M4
Macrocell
M4
O2
I/O Cell
I/O2
C5
M5
Macrocell
M5
C6
M6
Macrocell
M6
O3
I/O Cell
I/O3
Central Switch Matrix
C7
M7
Macrocell
M7
C8
M8
Macrocell
M8
Output Switch Matrix
Logic Allocator
O4
I/O Cell
I/O4
C9
M9
Macrocell
M9
C10
M10
Macrocell
M10
O5
I/O Cell
I/O5
C11
M11
Macrocell
M11
C12
M12
Macrocell
M12
O6
I/O Cell
I/O6
C13
M13
Macrocell
M13
C14
M14
Macrocell
M14
O7
I/O Cell
I/O7
C15
M15
Macrocell
M15
17 16 24
Input Switch Matrix
16
17469E-3
Figure 1. MACH435 PAL Block
MACH435-12/15/20, Q-20/25
7
ABSOLUTE MAXIMUM RATINGS
Storage Temperature . . . . . . . . . . . -65C to +150C Ambient Temperature with Power Applied . . . . . . . . . . . . . -55C to +125C Supply Voltage with Respect to Ground . . . . . . . . . . . . . -0.5 V to +7.0 V DC Input Voltage . . . . . . . . . . . . -0.5 V to VCC +0.5 V DC Output or I/O Pin Voltage . . . . . . . . . . . . . -0.5 V to VCC +0.5 V Static Discharge Voltage . . . . . . . . . . . . . . . . . 2001 V Latchup Current (TA = 0C to +70C) . . . . . . . . . . . . . . . . . . . . 200 mA
OPERATING RANGES
Commercial (C) Devices Temperature (TA) Operating in Free Air . . . . . . . . . . . . . . . . . . . . . . . 0C to +70C Supply Voltage (VCC) with Respect to Ground . . . . . . . . . . . . +4.75 V to +5.25 V
Operating ranges define those limits between which the functionality of the device is guaranteed. Stresses above those listed under Absolute Maximum Ratings may cause permanent device failure. Functionality at or above these limits is not implied. Exposure to Absolute Maximum Ratings for extended periods may affect device reliability. Programming conditions may differ.
DC CHARACTERISTICS over COMMERCIAL operating ranges unless otherwise specified
Parameter Symbol VOH VOL VIH VIL IIH IIL IOZH IOZL ISC ICC Parameter Description Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage Input HIGH Leakage Current Input LOW Leakage Current Off-State Output Leakage Current HIGH Off-State Output Leakage Current LOW Output Short-Circuit Current Supply Current (Typical) Test Conditions IOH = -3.2 mA, VCC = Min VIN = VIH or VIL IOL = 24 mA, VCC = Min VIN = VIH or VIL (Note 1) Guaranteed Input Logical HIGH Voltage for all Inputs (Note 2) Guaranteed Input Logical LOW Voltage for all Inputs (Note 2) VIN = 5.25 V, VCC = Max (Note 3) VIN = 0 V, VCC = Max (Note 3) VOUT = 5.25 V, VCC = Max VIN = VIH or VIL (Note 3) VOUT = 0 V, VCC = Max VIN = VIH or VIL (Note 3) VOUT = 0.5 V, VCC = Max (Note 4) VIN = 0 V, Outputs Open (IOUT = 0 mA) VCC = 5.0 V, f =25 MHz, TA = 25C (Note 5) -30 255 2.0 0.8 10 -100 10 -100 -160 Min 2.4 0.5 Typ Max Unit V V V V A A A A mA mA
CAPACITANCE (Note 6)
Parameter Symbol CIN COUT Parameter Description Input Capacitance Output Capacitance Test Conditions VIN = 2.0 V VOUT = 2.0 V VCC = 5.0 V, TA = 25C, f = 1 MHz Typ 6 8 Unit pF pF
Notes: 1. 2. 3. 4. Total IOL for one PAL block should not exceed 128 mA. These are absolute values with respect to device ground and all overshoots due to system or tester noise are included. I/O pin leakage is the worst case of IIL and IOZL (or IIH and IOZH). Not more than one output should be shorted at a time and duration of the short-circuit should not exceed one second. VOUT = 0.5 V has been chosen to avoid test problems caused by tester ground degradation. 5. Measured with a 16-bit up/down counter pattern. This pattern is programmed in each PAL block and capable of being loaded, enabled, and reset. 6. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified where capacitance may be affected.
8
MACH435-12 (Com'l)
SWITCHING CHARACTERISTICS over COMMERCIAL operating ranges (Note 1)
Parameter Symbol tPD tSA -12 Parameter Description Input, I/O, or Feedback to Combinatorial Output Setup Time from Input, I/O, or Feedback to Product Term Clock Register Data Hold Time Using Product Term Clock Product Term Clock to Output Product Term, Clock Width LOW HIGH External Feedback fMAXA Maximum Frequency Using Product Term Clock (Note 2) Internal Feedback (fCNTA) No Feedback (Note 3) tSS tHS tCOS tWLS tWHS External Feedback fMAXS Maximum Frequency Using Global Clock (Note 2) Setup Time from Input, I/O, or Feedback to Global Clock Register Data Hold Time Using Global Clock Global Clock to Output Global Clock Width LOW HIGH D-type T-type D-type Internal Feedback (fCNTA) No Feedback (Note 3) tSLA tHLA tGOA tGWA tSLS tHLS tGOS tGWS tPDL tSIR tHIR tICO Setup Time from Input, I/O, or Feedback to Product Term Clock Latch Data Hold Time Using Product Term Clock Product Term Gate to Output Product Term Gate Width LOW (for LOW transparent) or HIGH (for HIGH transparent) Setup Time from Input, I/O, or Feedback to Global Gate Latch Data Hold Time Using Global Gate Gate to Output Global Gate Width LOW (for LOW transparent) or HIGH (for HIGH transparent) Input, I/O, or Feedback to Output Through Transparent Input or Output Latch Input Register Setup Time Input Register Hold Time Input Register Clock to Combinatorial Output 2 3 18 6 6 8 0 10 T-type D-type T-type D-type T-type D-type T-type D-type T-type Min 3 5 6 5 4 8 8 52.6 50 58.8 55.6 62.5 7 8 0 2 6 6 66.7 62.5 83.3 76.9 83.3 5 5 16 8 14 Max 12 Unit ns ns ns ns ns ns ns MHz MHz MHz MHz MHz ns ns ns ns ns ns MHz MHz MHz MHz MHz ns ns ns ns ns ns ns ns
tHA tCOA tWLA tWHA
14
ns ns ns ns
MACH435-12 (Com'l)
9
SWITCHING CHARACTERISTICS over COMMERCIAL operating ranges (Note 1) (continued)
Parameter Symbol tICS tWICL tWICH fMAXIR tSIL tHIL tIGO tIGOL Input Register Clock Width Maximum Input Register Frequency Input Latch Setup Time Input Latch Hold Time Input Latch Gate to Combinatorial Output Input Latch Gate to Output Through Transparent Output Latch Setup Time from Input, I/O, or Feedback Through Transparent Input Latch to Product Term Output Latch Gate Input Latch Gate to Output Latch Setup Using Product Term Output Latch Gate Setup Time from Input, I/O, or Feedback Through Transparent Input Latch to Global Output Latch Gate Input Latch Gate to Output Latch Setup Using Global Output Latch Gate Input Latch Gate Width LOW Input, I/O, or Feedback to Output Through Transparent Input and Output Latches Asynchronous Reset to Registered or Latched Output Asynchronous Reset Width (Note 1) Asynchronous Reset Recovery Time (Note 1) Asynchronous Preset to Registered or Latched Output Asynchronous Preset Width (Note 1) Asynchronous Preset Recovery Time (Note 1) Input, I/O, or Feedback to Output Enable Input, I/O, or Feedback to Output Disable 12 8 2 2 12 12 12 10 16 4 4 -12 Parameter Description Input Register Clock to Output Register Setup D-type T-type LOW HIGH Min 9 10 6 6 83.3 2 3 16 18 Max Unit ns ns ns ns MHz ns ns ns ns ns ns
tSLLA tIGSA tSLLS tIGSS tWIGL tPDLL tAR tARW tARR tAP tAPW tAPR tEA tER
9 9 6 16 16
ns ns ns ns ns ns ns ns ns ns ns ns
Notes: 1. See Switching Test Circuit at the end of this Data Book for test conditions. 2. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified where frequency may be affected. 3. This parameter does not apply to flip-flops in the emulated mode since the feedback path is required for emulation.
10
MACH435-12 (Com'l)
ABSOLUTE MAXIMUM RATINGS
Storage Temperature . . . . . . . . . . . -65C to +150C Ambient Temperature with Power Applied . . . . . . . . . . . . . -55C to +125C Supply Voltage with Respect to Ground . . . . . . . . . . . . . -0.5 V to +7.0 V DC Input Voltage . . . . . . . . . . . . -0.5 V to VCC +0.5 V DC Output or I/O Pin Voltage . . . . . . . . . . . . . -0.5 V to VCC +0.5 V Static Discharge Voltage . . . . . . . . . . . . . . . . . 2001 V Latchup Current (TA = 0C to +70C) . . . . . . 200 mA
Stresses above those listed under Absolute Maximum Ratings may cause permanent device failure. Functionality at or above these limits is not implied. Exposure to Absolute Maximum Ratings for extended periods may affect device reliability. Programming conditions may differ.
OPERATING RANGES
Commercial (C) Devices Temperature (TA) Operating in Free Air . . . . . . . . . . . . . . . . . . . . . . . 0C to +70C Supply Voltage (VCC) with Respect to Ground . . . . . . . . . . . . +4.75 V to +5.25 V
Operating ranges define those limits between which the functionality of the device is guaranteed.
DC CHARACTERISTICS over COMMERCIAL operating ranges unless otherwise specified
Parameter Symbol VOH VOL VIH VIL IIH IIL IOZH IOZL ISC ICC Parameter Description Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage Input HIGH Leakage Current Input LOW Leakage Current Off-State Output Leakage Current HIGH Off-State Output Leakage Current LOW Output Short-Circuit Current Supply Current Test Conditions IOH = -3.2 mA, VCC = Min VIN = VIH or VIL IOL = 24 mA, VCC = Min VIN = VIH or VIL (Note 1) Guaranteed Input Logical HIGH Voltage for all Inputs (Note 2) Guaranteed Input Logical LOW Voltage for all Inputs (Note 2) VIN = 5.25 V, VCC = Max (Note 3) VIN = 0 V, VCC = Max (Note 3) VOUT = 5.25 V, VCC = Max VIN = VIH or VIL (Note 3) VOUT = 0 V, VCC = Max VIN = VIH or VIL (Note 3) VOUT = 0.5 V, VCC = Max (Note 4) VIN = 0 V, Outputs Open (IOUT = 0 mA), VCC = 5.0 V, f =25 MHz, TA = 25C (Note 5) -30 255 2.0 0.8 10 -100 10 -100 -160 Min 2.4 0.5 Typ Max Unit V V V V A A A A mA mA
CAPACITANCE (Note 6)
Parameter Symbol CIN COUT Parameter Description Input Capacitance Output Capacitance Test Conditions VIN = 2.0 V VOUT = 2.0 V VCC = 5.0 V, TA = 25C, f = 1 MHz Typ 6 8 Unit pF pF
Notes: 1. Total IOL for one PAL block should not exceed 128 mA. 2. These are absolute values with respect to device ground and all overshoots due to system or tester noise are included. 3. I/O pin leakage is the worst case of IIL and IOZL (or IIH and IOZH ). 4. Not more than one output should be shorted at a time and duration of the short-circuit should not exceed one second. VOUT = 0.5 V has been chosen to avoid test problems caused by tester ground degradation. 5. Measured with a 16-bit up/down counter pattern. This pattern is programmed in each PAL Block and capable of being loaded, enabled, and reset. An actual ICC value can be calculated by using the "Typical Dynamic ICCCharacteristics" Chart towards the end of this data sheet. 6. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified where capacitance may be affected.
MACH435-15/20 (Com'l)
11
SWITCHING CHARACTERISTICS over COMMERCIAL operating ranges (Note 1)
Parameter Symbol Parameter Description tPD tSA Input, I/O, or Feedback to Combinatorial Output (Note 2) Setup Time from Input, I/O, or Feedback to Product Term Clock Register Data Hold Time Using Product Term Clock Product Term Clock to Output (Note 2) Product Term, Clock Width LOW HIGH D-type External Feedback 1/(tSA + tCOA) fMAXA Maximum Frequency Using Product Term Clock (Note 3) T-type Internal Feedback (fCNTA) No Feedback (Note 4) 1/(tWLA + tWHA) D-type T-type D-type T-type 37 47.6 45.4 55.6 10 11 0 2 LOW Global Clock Width tWHS External Feedback 1/(tSS + tCOS) fMAXS Maximum Frequency Using Global Clock (Note 3) HIGH D-type T-type D-type Internal Feedback (fCNTS) No Feedback (Note 4) tSLA tHLA tGOA tGWA tSLS tHLS tGOS tGWS tPDL tSIR tHIR tICO 1/(tWLS + tWHS) T-type 6 50 47.6 66.6 62.5 83.3 8 8 19 9 10 0 11 6 8 12 13 0 12 8 40 38.5 50 47.6 62.5 10 10 22 ns MHz MHz MHz MHz MHz ns ns ns ns ns ns ns ns 6 10 30.3 37 35.7 41.7 13 14 0 2 8 12 MHz MHz MHz MHz ns ns ns ns ns D-type T-type -15 Min 3 8 9 8 4 9 9 38.5 18 Max 15 Min 3 10 11 10 4 12 12 31.2 22 -20 Max 20 Unit ns ns ns ns ns ns ns MHz
tHA tCOA tWLA tWHA
tSS
Setup Time from Input, I/O, or Feedback to Global Clock Register Data Hold Time Using Global Clock Global Clock to Output (Note 2)
tHS tCOS tWLS
Setup Time from Input, I/O, or Feedback to Product Term Clock Latch Data Hold Time Using Product Term Clock Product Term Gate to Output (Note 2) Product Term Gate Width LOW (for LOW transparent) or HIGH (for HIGH transparent) Setup Time from Input, I/O, or Feedback to Global Gate Latch Data Hold Time Using Global Gate Gate to Output (Note 2) Global Gate Width LOW (for LOW transparent) or HIGH (for HIGH transparent) Input, I/O, or Feedback to Output Through Transparent Input or Output Latch Input Register Setup Time Input Register Hold Time Input Register Clock to Combinatorial Output
17 2 4 20 2 5
22
ns ns ns
25
ns
12
MACH435-15/20 (Com'l)
SWITCHING CHARACTERISTICS over COMMERCIAL operating ranges (Note 1) (continued)
Parameter Symbol Parameter Description tICS Input Register Clock to Output Register Setup D-type T-type tWICL Input Register Clock Width tWICH fMAXIR tSIL tHIL tIGO tIGOL Maximum Input Register Frequency Input Latch Setup Time Input Latch Hold Time Input Latch Gate to Combinatorial Output Input Latch Gate to Output Through Transparent Output Latch Setup Time from Input, I/O, or Feedback Through Transparent Input Latch to Product Term Output Latch Gate Input Latch Gate to Output Latch Setup Using Product Term Output Latch Gate Setup Time from Input, I/O, or Feedback Through Transparent Input Latch to Global Output Latch Gate Input Latch Gate to Output Latch Setup Using Global Output Latch Gate Input Latch Gate Width LOW Input, I/O, or Feedback to Output Through Transparent Input and Output Latches Asynchronous Reset to Registered or Latched Output Asynchronous Reset Width (Note 3) Asynchronous Reset Recovery Time (Note 3) Asynchronous Preset to Registered or Latched Output Asynchronous Preset Width (Note 3) Asynchronous Preset Recovery Time (Note 3) Input, I/O, or Feedback to Output Enable (Note 2) Input, I/O, or Feedback to Output Disable (Note 2) 15 15 2 2 15 15 15 15 20 20 20 2 2 20 20 HIGH 1/(tWICL + tWICH) 6 83.3 2 4 20 22 8 62.5 2 5 25 27 ns MHz ns ns ns ns LOW -15 Min 15 16 6 Max Min 20 21 8 -20 Max Unit ns ns ns
tSLLA tIGSA tSLLS tIGSS tWIGL tPDLL tAR tARW tARR tAP tAPW tAPR tEA tER
10 14 12 16 6 19 20
12 19 16 21 8 24 25 20 20 25
ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Notes: 1. See Switching Test Circuit at the end of this Data Book for test conditions. 2. Parameters measured with 32 outputs switching. 3. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified where frequency may be affected. 4. This parameter does not apply to flip-flops in the emulated mode since the feedback path is required for emulation.
MACH435-15/20 (Com'l)
13
ABSOLUTE MAXIMUM RATINGS
Storage Temperature . . . . . . . . . . . -65C to +150C Ambient Temperature with Power Applied . . . . . . . . . . . . . -55C to +125C Supply Voltage with Respect to Ground . . . . . . . . . . . . . -0.5 V to +7.0 V DC Input Voltage . . . . . . . . . . . . -0.5 V to VCC +0.5 V DC Output or I/O Pin Voltage . . . . . . . . . . . . . -0.5 V to VCC +0.5 V Static Discharge Voltage . . . . . . . . . . . . . . . . . 2001 V Latchup Current (TA = 0C to +70C) . . . . . . . . . . . . . . . . . . . . 200 mA
OPERATING RANGES
Commercial (C) Devices Temperature (TA) Operating in Free Air . . . . . . . . . . . . . . . . . . . . . . . 0C to +70C Supply Voltage (VCC) with Respect to Ground . . . . . . . . . . . . +4.75 V to +5.25 V
Operating ranges define those limits between which the functionality of the device is guaranteed. Stresses above those listed under Absolute Maximum Ratings may cause permanent device failure. Functionality at or above these limits is not implied. Exposure to Absolute Maximum Ratings for extended periods may affect device reliability. Programming conditions may differ.
DC CHARACTERISTICS over COMMERCIAL operating ranges unless otherwise specified
Parameter Symbol VOH VOL VIH VIL IIH IIL IOZH IOZL ISC ICC Parameter Description Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage Input HIGH Leakage Current Input LOW Leakage Current Off-State Output Leakage Current HIGH Off-State Output Leakage Current LOW Output Short-Circuit Current Supply Current (Typical) Test Conditions IOH = -3.2 mA, VCC = Min VIN = VIH or VIL IOL = 24 mA, VCC = Min VIN = VIH or VIL (Note 1) Guaranteed Input Logical HIGH Voltage for all Inputs (Note 2) Guaranteed Input Logical LOW Voltage for all Inputs (Note 2) VIN = 5.25 V, VCC = Max (Note 3) VIN = 0 V, VCC = Max (Note 3) VOUT = 5.25 V, VCC = Max VIN = VIH or VIL (Note 3) VOUT = 0 V, VCC = Max VIN = VIH or VIL (Note 3) VOUT = 0.5 V, VCC = Max (Note 4) VIN = 0 V, Outputs Open (IOUT = 0 mA) VCC = 5.0 V, f =25 MHz, TA = 25C (Note 5) -30 115 2.0 0.8 10 -100 10 -100 -160 Min 2.4 0.5 Typ Max Unit V V V V A A A A mA mA
CAPACITANCE (Note 6)
Parameter Symbol CIN COUT Parameter Description Input Capacitance Output Capacitance Test Conditions VIN = 2.0 V VOUT = 2.0 V VCC = 5.0 V, TA = 25C, f = 1 MHz Typ 6 8 Unit pF pF
Notes: 1. 2. 3. 4. Total IOL for one PAL block should not exceed 128 mA. These are absolute values with respect to device ground and all overshoots due to system or tester noise are included. I/O pin leakage is the worst case of IIL and IOZL (or IIH and IOZH). Not more than one output should be shorted at a time and duration of the short-circuit should not exceed one second. VOUT = 0.5 V has been chosen to avoid test problems caused by tester ground degradation. 5. Measured with a 16-bit up/down counter pattern. This pattern is programmed in each PAL block and capable of being loaded, enabled, and reset. 6. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified where capacitance may be affected.
14
MACH435Q-20 (Com'l)
SWITCHING CHARACTERISTICS over COMMERCIAL operating ranges (Note 1)
Parameter Symbol tPD tSA -20 Parameter Description Input, I/O, or Feedback to Combinatorial Output Setup Time from Input, I/O, or Feedback to Product Term Clock tHA tCOA tWLA tWHA Register Data Hold Time Using Product Term Clock Product Term Clock to Output Product Term, Clock Width LOW HIGH D-type External Feedback fMAXA Maximum Frequency Using Product Term Clock (Note 2) Internal Feedback (fCNTA) No Feedback (Note 3) tSS tHS tCOS tWLS tWHS Setup Time from Input, I/O, or Feedback to Global Clock Register Data Hold Time Using Global Clock Global Clock to Output Global Clock Width LOW HIGH D-type External Feedback fMAXS Maximum Frequency Using Global Clock (Note 2) T-type D-type Internal Feedback (fCNTA) No Feedback (Note 3) tSLA tHLA tGOA tGWA tSLS tHLS tGOS tGWS tPDL tSIR tHIR tICO Setup Time from Input, I/O, or Feedback to Product Term Clock Latch Data Hold Time Using Product Term Clock Product Term Gate to Output Product Term Gate Width LOW (for LOW transparent) or HIGH (for HIGH transparent) Setup Time from Input, I/O, or Feedback to Global Gate Latch Data Hold Time Using Global Gate Gate to Output Global Gate Width LOW (for LOW transparent) or HIGH (for HIGH transparent) Input, I/O, or Feedback to Output Through Transparent Input or Output Latch Input Register Setup Time Input Register Hold Time Input Register Clock to Combinatorial Output 2 4 22 8 12 13 0 12 T-type D-type T-type T-type D-type T-type D-type T-type Min 3 10 11 16 5 12 12 33.3 37.2 35.7 34.5 41.7 13 14 0 2 8 8 40.0 38.5 47.6 43.5 62.5 8 8 22 12 22 Max 20 Unit ns ns ns ns ns ns ns MHz MHz MHz MHz MHz ns ns ns ns ns ns MHz MHz MHz MHz MHz ns ns ns ns ns ns ns ns
22
ns ns ns ns
MACH435Q-20 (Com'l)
15
SWITCHING CHARACTERISTICS over COMMERCIAL operating ranges (Note 1) (continued)
Parameter Symbol tICS tWICL tWICH fMAXIR tSIL tHIL tIGO tIGOL Input Register Clock Width Maximum Input Register Frequency Input Latch Setup Time Input Latch Hold Time Input Latch Gate to Combinatorial Output Input Latch Gate to Output Through Transparent Output Latch Setup Time from Input, I/O, or Feedback Through Transparent Input Latch to Product Term Output Latch Gate Input Latch Gate to Output Latch Setup Using Product Term Output Latch Gate Setup Time from Input, I/O, or Feedback Through Transparent Input Latch to Global Output Latch Gate Input Latch Gate to Output Latch Setup Using Global Output Latch Gate Input Latch Gate Width LOW or HIGH Input, I/O, or Feedback to Output Through Transparent Input and Output Latches Asynchronous Reset to Registered or Latched Output Asynchronous Reset Width (Note 1) Asynchronous Reset Recovery Time (Note 1) Asynchronous Preset to Registered or Latched Output Asynchronous Preset Width (Note 1) Asynchronous Preset Recovery Time (Note 1) Input, I/O, or Feedback to Output Enable Input, I/O, or Feedback to Output Disable 20 15 2 2 20 20 20 15 25 12 10 -20 Parameter Description Input Register Clock to Output Register Setup D-type T-type LOW HIGH Min 15 17 8 8 62.5 2 2.5 22 24 Max Unit ns ns ns ns MHz ns ns ns ns ns ns
tSLLA tIGSA tSLLS tIGSS tWIGL tPDLL tAR tARW tARR tAP tAPW tAPR tEA tER
15 15 8 24 25
ns ns ns ns ns ns ns ns ns ns ns ns
Notes: 1. See Switching Test Circuit at the end of this Data Book for test conditions. 2. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified where frequency may be affected. 3. This parameter does not apply to flip-flops in the emulated mode since the feedback path is required for emulation.
16
MACH435Q-20 (Com'l)
ABSOLUTE MAXIMUM RATINGS
Storage Temperature . . . . . . . . . . . -65C to +150C Ambient Temperature with Power Applied . . . . . . . . . . . . . -55C to +125C Supply Voltage with Respect to Ground . . . . . . . . . . . . . -0.5 V to +7.0 V DC Input Voltage . . . . . . . . . . . -0.5 V to VCC +0.5 V DC Output or I/O Pin Voltage . . . . . . . . . . . . -0.5 V to VCC +0.5 V Static Discharge Voltage . . . . . . . . . . . . . . . . . 2001 V Latchup Current (TA = 0C to +70C) . . . . . . . . . . . . . . . . . . . . 200 mA
OPERATING RANGES
Commercial (C) Devices Temperature (TA) Operating in Free Air . . . . . . . . . . . . . . . . . . . . . . . 0C to +70C Supply Voltage (VCC) with Respect to Ground . . . . . . . . . . . . +4.75 V to +5.25 V
Operating ranges define those limits between which the functionality of the device is guaranteed. Stresses above those listed under Absolute Maximum Ratings may cause permanent device failure. Functionality at or above these limits is not implied. Exposure to Absolute Maximum Ratings for extended periods may affect device reliability. Programming conditions may differ.
DC CHARACTERISTICS over COMMERCIAL operating ranges unless otherwise specified
Parameter Symbol VOH VOL VIH VIL IIH Parameter Description Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage Input HIGH Leakage Current Input LOW Leakage Current Off-State Output Leakage Current HIGH Off-State Output Leakage Current LOW Output Short-Circuit Current Supply Current Test Conditions IOH = -3.2 mA, VCC = Min VIN = VIH or VIL IOL = 24 mA, VCC = Min VIN = VIH or VIL (Note 1) Guaranteed Input Logical HIGH Voltage for all Inputs (Note 2) Guaranteed Input Logical LOW Voltage for all Inputs (Note 2) VIN = 5.25 V, VCC = Max (Note 3) VIN = 0 V, VCC = Max (Note 3) VOUT = 5.25 V, VCC = Max VIN = VIH or VIL (Note 3) VOUT = 0 V, VCC = Max VIN = VIH or VIL (Note 3) VOUT = 0.5 V, VCC = Max (Note 4) VIN = 0 V, Outputs Open (IOUT = 0 mA), VCC = 5.0 V, f=25 MHz, TA = 25C, (Note 5) -30 115 2.0 0.8 10 -100 10 -100 -160 Min 2.4 0.5 Typ Max Unit V V V V A A A A mA mA
IIL
IOZH IOZL ISC ICC
CAPACITANCE (Note 1)
Parameter Symbol CIN COUT Parameter Description Input Capacitance Output Capacitance Test Conditions VIN = 2.0 V VOUT = 2.0 V VCC = 5.0 V, TA = 25C, f = 1 MHz Typ 6 8 Unit pF pF
Notes: 1. Total IOL for one PAL block should not exceed 128 mA. 2. These are absolute values with respect to device ground and all overshoots due to system or tester noise are included. 3. I/O pin leakage is the worst case of IIL and IOZL (or IIH and IOZH). 4. Not more than one output should be shorted at a time and duration of the short-circuit should not exceed one second. VOUT = 0.5 V has been chosen to avoid test problems caused by tester ground degradation. 5. Measured with a 16-bit up/down counter pattern. This pattern is programmed in each PAL Block and capable of being loaded, erased, and reset. An actual ICC value can be calculated by using the "Typical Dynamic ICC Characteristics" Chart towards the end of the this data sheet. 6. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified where capacitance may be affected.
MACH435Q-25 (Com'l)
17
SWITCHING CHARACTERISTICS over COMMERCIAL operating ranges (Note 1)
Parameter Symbol Parameter Description tPD tSA Input, I/O, or Feedback to Combinatorial Output (Note 2) Setup Time from Input, I/O, or Feedback to Product Term Clock Register Data Hold Time Using Product Term Clock Product Term Clock to Output (Note 2) Product Term, Clock Width LOW HIGH External Feedback fMAXA Maximum Frequency Using Product Term Clock (Note 3) 1/(tSA + tCOA) D-type T-type Internal Feedback (fCNTA) No Feedback (Note 4) 1/(tWLA + tWHA) D-type T-type D-type T-type D-type T-type -25 Min 3 18 19 18 4 19 19 21.7 21.3 24.4 23.8 26.3 20 21 0 2 LOW HIGH D-type External Feedback fMAXS Maximum Frequency Using Global Clock (Note 3) 1/(tSS + tCOS) T-type D-type Internal Feedback (fCNTS) T-type No Feedback (Note 4) tSLA tHLA tGOA tGWA tSLS tHLS tGOS tGWS tPDL tSIR tHIR tICO 1/(tSS + tHS) 35.7 50 18 18 29 19 20 0 21 8 MHz MHz ns ns ns ns ns ns ns ns 8 8 31.3 30.3 37 12 28 Max 25 Unit ns ns ns ns ns ns ns MHz MHz MHz MHz MHz ns ns ns ns ns ns MHz MHz MHz
tHA tCOA tWLA tWHA
tSS
Setup Time from Input, I/O, or Feedback to Global Clock Register Data Hold Time Using Global Clock Global Clock to Output (Note 2) Global Clock Width
tHS tCOS tWLS tWHS
Setup Time from Input, I/O, or Feedback to Product Term Clock Latch Data Hold Time Using Product Term Clock Product Term Gate to Output (Note 2) Product Term Gate Width LOW (for LOW transparent) or HIGH (for HIGH transparent) Setup Time from Input, I/O, or Feedback to Global Gate Latch Data Hold Time Using Global Gate Gate to Output (Note 2) Global Gate Width LOW (for LOW transparent) or HIGH (for HIGH transparent) Input, I/O, or Feedback to Output Through Transparent Input or Output Latch Input Register Setup Time Input Register Hold Time Input Register Clock to Combinatorial Output
27 5 5 30
ns ns ns ns
18
MACH435Q-25 (Com'l)
SWITCHING CHARACTERISTICS over COMMERCIAL operating ranges (Note 1) (continued)
Parameter Symbol Parameter Description tICS Input Register Clock to Output Register Setup D-type T-type tWICL Input Register Clock Width tWICH fMAXIR tSIL tHIL tIGO tIGOL Maximum Input Register Frequency Input Latch Setup Time Input Latch Hold Time Input Latch Gate to Combinatorial Output Input Latch Gate to Output Through Transparent Output Latch Setup Time from Input, I/O, or Feedback Through Transparent Input Latch to Product Term Output Latch Gate Input Latch Gate to Output Latch Setup Using Product Term Output Latch Gate Setup Time from Input, I/O, or Feedback Through Transparent Input Latch to Global Output Latch Gate Input Latch Gate to Output Latch Setup Using Global Output Latch Gate Input Latch Gate Width LOW or HIGH Input, I/O, or Feedback to Output Through Transparent Input and Output Latches Asynchronous Reset to Registered or Latched Output Asynchronous Reset Width (Note 3) Asynchronous Reset Recovery Time (Note 3) Asynchronous Preset to Registered or Latched Output Asynchronous Preset Width (Note 3) Asynchronous Preset Recovery Time (Note 3) Input, I/O, or Feedback to Output Enable (Note 2) Input, I/O, or Feedback to Output Disable (Note 2) 25 25 2 2 25 25 25 25 30 1/(tWICL + tWICH) HIGH 8 62.5 5 5 30 32 ns MHz ns ns ns ns LOW -25 Min 25 26 8 Max Unit ns ns ns
tSLLA tIGSA tSLLS tIGSS tWIGL tPDLL tAR tARW tARR tAP tAPW tAPR tEA tER
20 24 22 26 8 29 30
ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Notes: 1. See Switching Test Circuit at the end of this Data Book for test conditions. 2. Parameters measured with 32 outputs switching. 3. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified where frequency may be affected. 4. This parameter does not apply to flip-flops in the emulated mode since the feedback path is required for emulation.
MACH435Q-25 (Com'l)
19
TYPICAL CURRENT VS. VOLTAGE (I-V) CHARACTERISTICS
VCC = 5.0 V, TA = 25C
IOL (mA) 80 60 40 20 VOL (V) -1.0 -0.8 -0.6 -0.4 -0.2 -20 -40 -60 -80
17469E-4
.2
.4
.6
.8
1.0
Output, LOW
IOH (mA) 25 1 -3 -2 -1 -25 -50 -75 -100 -125 -150
17469E-5
2
3
4
5 VOH (V)
Output, HIGH II (mA)
20
VI (V)
-2 -1 -20 -40 -60 -80 -100
17469E-6
1
2
3
4
5
Input
20
MACH435-12/15/20, Q-20/25
TYPICAL ICC CHARACTERISTICS VCC = 5 V, TA = 25C
325 300 275 250 225 200 175 ICC (mA) 150 125 100 75 50 25 0 0 10 20 30 40 50 60 70
17469E-7
MACH435
MACH435Q
Frequency (MHz)
The selected "typical" pattern is a 16-bit up/down counter. This pattern is programmed in each PAL block and is capable of being loaded, enabled, and reset. Maximum frequency shown uses internal feedback and a D-type register.
MACH435-12/15/20, Q-20/25
21
TYPICAL THERMAL CHARACTERISTICS
Measured at 25C ambient. These parameters are not tested.
Parameter Symbol jc ja jma Parameter Description Thermal impedance, junction to case Thermal impedance, junction to ambient Thermal impedance, junction to ambient with air flow 200 lfpm air 400 lfpm air 600 lfpm air 800 lfpm air Typ PLCC 5 20 17 14 12 10 Unit C/W C/W C/W C/W C/W C/W
Plastic jc Considerations The data listed for plastic jc are for reference only and are not recommended for use in calculating junction temperatures. The heat-flow paths in plastic-encapsulated devices are complex, making the jc measurement relative to a specific location on the package surface. Tests indicate this measurement reference point is directly below the die-attach area on the bottom center of the package. Furthermore, jc tests on packages are performed in a constant-temperature bath, keeping the package surface at a constant temperature. Therefore, the measurements can only be used in a similar environment.
22
MACH435-12/15/20, Q-20/25
SWITCHING WAVEFORMS
Input, I/O, or Feedback
VT tPD
Combinatorial Output
VT
17469E-8
Combinatorial Output
Input, I/O, or Feedback tS Clock VT tCO Registered Output
VT tH
Input, I/O, or Feedback tSL Gate tPDL VT
17469E-9
VT tHL VT tGO VT
17469E-10
Latched Out
Registered Output
Latched Output (MACH 2, 3, and 4)
tWH Clock tWL
17469E-11
Gate tGWS
VT
17469E-12
Clock Width
Gate Width (MACH 2, 3, and 4)
Registered Input tSIR Input Register Clock Combinatorial Output VT tICO
VT tHIR
Registered Input Input Register Clock VT Output Register Clock
VT
VT
tICS
VT
17469E-14
17469E-13
Registered Input (MACH 2 and 4)
Input Register to Output Register Setup (MACH 2 and 4)
Notes: 1. VT = 1.5 V. 2. Input pulse amplitude 0 V to 3.0 V. 3. Input rise and fall times 2 ns-4 ns typical.
MACH435-12/15/20, Q-20/25
23
SWITCHING WAVEFORMS
Latched In tSIL Gate
VT tHIL VT tIGO
Combinatorial Output
VT
17469E-15
Latched Input (MACH 2 and 4)
tPDLL Latched In Latched Out Input Latch Gate tIGOL VT
VT
tIGS Output Latch Gate
tSLL VT
17469E-16
Latched Input and Output (MACH 2, 3, and 4)
Notes: 1. VT = 1.5 V. 2. Input pulse amplitude 0 V to 3.0 V. 3. Input rise and fall times 2 ns-4 ns typical.
24
MACH435-12/15/20, Q-20/25
SWITCHING WAVEFORMS
tWICH Clock tWICL
17469E-17
VT
Input Latch Gate tWIGL
VT
17469E-18
Input Register Clock Width (MACH 2 and 4)
Input Latch Gate Width (MACH 2 and 4)
tARW Input, I/O, or Feedback tAR Registered Output VT tARR Clock VT
17469E-19
tAPW VT Input, I/O, or Feedback tAP Registered Output VT tAPR Clock VT
17469E-20
VT
Asynchronous Reset
Asynchronous Preset
Input, I/O, or Feedback tER Outputs VOH - 0.5V VOL + 0.5V
VT tEA VT
17469E-21
Output Disable/Enable
Notes: 1. VT = 1.5 V. 2. Input pulse amplitude 0 V to 3.0 V. 3. Input rise and fall times 2 ns-4 ns typical.
MACH435-12/15/20, Q-20/25
25
KEY TO SWITCHING WAVEFORMS
WAVEFORM INPUTS Must be Steady May Change from H to L May Change from L to H Don't Care, Any Change Permitted Does Not Apply OUTPUTS Will be Steady Will be Changing from H to L Will be Changing from L to H Changing, State Unknown Center Line is HighImpedance "Off" State
KS000010-PAL
SWITCHING TEST CIRCUIT
5V
S1
R1 Output R2 Test Point
CL
17469E-22
Commercial Specification tPD, tCO tEA tER S1 Closed Z H: Open Z L: Closed H Z: Open L Z: Closed 35 pF 300 5 pF 390 CL R1 R2
Measured Output Value 1.5 V 1.5 V H Z: VOH - 0.5 V L Z: VOL + 0.5 V
*Switching several outputs simultaneously should be avoided for accurate measurement.
26
MACH435-12/15/20, Q-20/25
ENDURANCE CHARACTERISTICS
The MACH families are manufactured using our advanced Electrically Erasable process. This technology uses an EE cell to replace the fuse link used in bipolar parts. As a result, the device can be erased and reprogrammed, a feature which allows 100% testing at the factory.
Endurance Characteristics
Parameter Symbol Parameter Description Min 10 tDR N Min Pattern Data Retention Time Max Reprogramming Cycles 20 100 Units Years Years Cycles Test Conditions Max Storage Temperature Max Operating Temperature Normal Programming Conditions
28
MACH435-12/15/20, Q-20/25
INPUT/OUTPUT EQUIVALENT SCHEMATICS
VCC
100 k 1 k VCC
ESD Protection
Input
VCC
VCC
100 k
1 k
Preload Circuitry
Feedback Input
17469E-24
I/O
MACH435-12/15/20, Q-20/25
29
POWER-UP RESET
The MACH devices have been designed with the capability to reset during system power-up. Following powerup, all flip-flops will be reset to LOW. The output state will depend on the logic polarity. This feature provides extra flexibility to the designer and is especially valuable in simplifying state machine initialization. A timing diagram and parameter table are shown below. Due to the synchronous operation of the power-up reset and the
Parameter Symbol tPR tS tWL
wide range of ways VCC can rise to its steady state, two conditions are required to insure a valid power-up reset. These conditions are: 1. The VCC rise must be monotonic. 2. Following reset, the clock input must not be driven from LOW to HIGH until all applicable input and feedback setup times are met.
Parameter Descriptions Power-Up Reset Time Input or Feedback Setup Time Clock Width LOW
Max 10 See Switching Characteristics
Unit s
VCC
Power 4V
tPR
Registered Output
tS
Clock
tWL
17469E-25
Power-Up Reset Waveform
30
MACH435-12/15/20, Q-20/25
USING PRELOAD AND OBSERVABILITY
In order to be testable, a circuit must be both controllable and observable. To achieve this, the MACH devices incorporate register preload and observability. In preload mode, each flip-flop in the MACH device can be loaded from the I/O pins, in order to perform functional testing of complex state machines. Register preload makes it possible to run a series of tests from a known starting state, or to load illegal states and test for proper recovery. This ability to control the MACH device's internal state can shorten test sequences, since it is easier to reach the state of interest. The observability function makes it possible to see the internal state of the buried registers during test by overriding each register's output enable and activating the output buffer. The values stored in output and buried registers can then be observed on the I/O pins. Without this feature, a thorough functional test would be impossible for any designs with buried registers. While the implementation of the testability features is fairly straightforward, care must be taken in certain instances to insure valid testing. One case involves asynchronous reset and preset. If the MACH registers drive asynchronous reset or preset lines and are preloaded in such a way that reset or preset are asserted, the reset or preset may remove the preloaded data. This is illustrated in Figure 2. Care should be taken when planning functional tests, so that states that will cause unexpected resets and presets are not preloaded. Another case to be aware of arises in testing combinatorial logic. When an output is configured as combinatorial, the observability feature forces the output into registered mode. When this happens, all product terms are forced to zero, which eliminates all combinatorial data. For a straight combinatorial output, the correct value will be restored after the preload or observe function, and there will be no problem. If the function implements a combinatorial latch, however, it relies on feedback to hold the correct value, as shown in Figure 3. As this value may change during the preload or observe operation, you cannot count on the data being correct after the operation. To insure valid testing in these cases, outputs that are combinatorial latches should not be tested immediately following a preload or observe sequence, but should first be restored to a known state. All MACH 2 devices support both preload and observability. Contact individual programming vendors in order to verify programmer support.
Reset Figure 3. Combinatorial Latch
17469E-27
Preloaded HIGH D Q1
Q
AR
Preloaded HIGH D Q2
Q
AR
On Preload Mode Off
Q1
AR
Q2
Figure 2. Preload/Reset Conflict
17469E-26
Set
MACH435-12/15/20, Q-20/25
31

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